In Global System for Mobile Communications (GSM) system, packets are alternately transmitted and received in different frequencies, i.e., after GSM system transmits a packet via a first frequency, a PLL is used to generate a second frequency for receiving another packet. In GSM standard, only a short period of approximately 300 μs is available for switching between transmitting. Therefore the PLL must to complete switching the clock signal from the first frequency to the second frequency or from the second frequency to the first frequency in the short period.
FIG. 1 shows a block diagram of a conventional PLL 100 comprising a phase detector 110, a charge pump 120, a low-pass filter 130, a VCO 140 and a frequency divider 150. Operations of the PLL 100 are to be described below. The phase detector 110 detects a phase difference between a reference signal Vref and a feedback signal Vfb to generate a phase difference signal ψ. The charge pump 120 generates a control voltage Vctrl according to the phase difference signal LP. The low-pass filterer 130 low-pass filters the control voltage Vctrl to generate a filtered control voltage V′ctrl. The VCO 140 generates an output voltage Vosc according to a voltage level of the filtered control voltage V′ctrl. The frequency divider 150 frequency divides the output signal Vosc to generate the feedback signal Vfb.
FIG. 2 shows a schematic diagram of an example of operations of the PLL 100. When a VCO curve of the VCO 140 is determined (i.e., a frequency of the feedback signal Vfb is equal to or approximates to the frequency of the reference signal Vref), and the phase of the reference voltage Vref in FIG. 1 lags the phase of the feedback signal Vfb, the control voltage Vctrl generated by the charge pump 120 according to the phase difference signal Δψ approximates 0V. That is, the VCO 140 decreases the frequency of the output signal Vosc to gradually narrow down the phase difference between the feedback signal Vfb and the reference signal Vref until the phase of the feedback signal Vfb leads the phase of the reference signal Vref (e.g., at a transition time point tA in FIG. 2), and at this point, the control voltage Vctrl gradually rises until it approximates to a target voltage level Vtar.
For example, supposing that a gain KVCO, of the VCO curve of the VCO 140 is 10 MHz/Volt, and a divisor of the frequency divider 50 is 300, the frequency of the output signal Vosc is 3.6 GHz, and an initial voltage of the control voltage Vctrl is 1V when the frequency of the reference voltage Vref is 12 MHz. When the phase of the reference voltage Vref is 360 degrees lag to the phase of the feedback signal, the control voltage Vctrl is decreased from 1V to 0V and outputted, and the frequency of the output signal is decreased from 3.6 GHz to 3.59 GHz, such that a time needed for the phase of the reference voltage Vref to reach the phase of the feedback signal Vfb (e.g., at time points t=0 to t=tA) is N cycles of the reference voltage Vref or N−1 cycles of the feedback signal Vfb, i.e., N*( 1/12 MHz)=(N−1)*( 300/3590 MHz), where N is equal to 360. When the phase of the reference voltage Vref is M degrees lag to the phase of the feedback signal, the time needed for the phase of the reference voltage Vref to reach the phase of the feedback signal Vfb is calculated as tx1=(M/360 degree)*360*( 1/12 MHz)=(M/360 degree)*30 μs. Therefore, when the phase of the reference voltage Vref about 360 degrees lags the phase of the feedback signal Vfb, the time period tx1 for the phase of the reference voltage Vref to reach the phase of the feedback signal Vfb is about 30 μs.
As mentioned above, there is only 300 μs available to switch between transmitting and receiving in the GSM system. In the period, and the transceiver need to calibrate a direct current (DC) offset and stabilize the PLL circuit. Generally speaking, the PLL 100 only has 150 μs to 170 μs for adjusting the phase of the feedback signal Vfb to equal the phase of the reference signal Vref. However, in the foregoing example, If the phase difference between the reference voltage Vref and the feedback signal Vfb approximates 360 degree, the PLL 100 requires the time period tx1 approximating to 30 μs for adjusting the phase of the reference voltage Vref to reach the phase of the feedback signal Vfb. In addition, the PLL 100 still needs a significant amount of time to converge the voltage level of the control voltage Vctrl (or the filtered control voltage V′ctrl) since accuracy of output signal Vosc compliant to the GSM specification needs to be less than 0.1 ppm. That is, a time period between the time point tA and a time point at which the locking process ends is quite long, such that the GSM specification may not be fulfilled for that a locking time of the PLL 100 is too long. Accordingly, the rather-long locking time results in an increase in power consumption as well as a decrease in time allowed for calibrations of other components, e.g., a calibration time for DC offset.
In addition, the conventional method for reducing the time period tx1 is shown in FIG. 2; however, the method mentioned in this article is only applicable to a situation where the phase difference between the reference voltage Vref and the feedback signal Vfb is within 180 degrees to 360 degrees. Therefore, the method in the article cannot significantly or comprehensively reduce the locking time of the PLL 100.